Non-volatile memory (NVM) is able to retain data when the power supply of a memory is cut off. The memory can be used to permanent store data such as parameters, configuration settings, long-term data storage, etc. Similarly, this kind of memory can be used to store instructions, or codes, for microprocessors, DSPs, or microcontrollers (MCU), etc. Non-volatile normally has three operations, read, write (or called program), and erase, for reading data, programming data, and erasing data before re-programming. Non-volatile memory can be an EPROM, EEPROM, or flash memory that can be programmed from 10K to 100K times, or Multiple-Time Programmable (MTP) to be programmed from a few times to a few hundred times, or One-Time Programmable (OTP) to be programmed one time only. The non-volatile memory can also be emerging memories such as PCRAM (Phase Change RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), or MRAM (Magnetic RAM).
One-Time-Programmable (OTP) is a particular type of non-volatile memory that can be programmed only once. An OTP memory allows the memory cells being programmed once and only once in their lifetime. OTP is generally based on standard CMOS processes and is usually embedded into an integrated circuit that allows each die in a wafer to be customized. There are many applications for OTP, such as memory repair, device trimming, configuration parameters, chip ID, security key, feature select, and PROM, etc.
FIG. 1 shows a conventional low-pin-count OTP memory 6. The OTP memory 6 has a shared pin 7 and a plurality of OTP cells that has a program pad 8 and an OTP element 5 for each cell. The OTP element is usually an electrical fuse that is fabricated from polysilicon, silicided polysilicon, or metal in CMOS processes. To program a fuse, a high voltage can be applied to the pad 8 to conduct a high current flowing through the OTP element 5 to break the fuse into a high resistance state. In 0.35 um CMOS, programming a polycide (i.e. polysilicon with silicide on top) fuse takes about 60 mA for 100 millisecond. The program current is so high that the shared pin or the nearby interlayer dielectric can be damaged. The area for a one-pad-one-fuse OTP cell is also very large, especially for low-pin-count chips.
FIG. 2(a) shows another conventional NVM cell 10. The NVM cell 10 has an NVM element 11 and a program selector 12. The NVM element 10 is coupled to a supply voltage V+ in one end and to a program selector 12 in the other end. The program selector 12 has the other end coupled to a second supply voltage V−. The program selector 12 can be turned on by asserting a control terminal Sel. The program selector 12 is usually constructed from a MOS device. The NVM element 11 is usually an electrical fuse based on polysilicon, silicided polysilicon, metal, a floating gate to store charges, or an anti-fuse based on gate oxide breakdown, etc.
FIG. 2(b) shows an NVM cell 15 using a diode as program selector, which is well suited for a low-pin-count NVMt. The NVM cell 15 has an NVM element 16 and a diode as a program selector 17. The NVM element 16 is coupled to a supply voltage V+ in one end and a program selector 17 in the other. The program selector 17 has the other end coupled to a second supply voltage V− as a select signal Sel. It is very desirable for the program selector 17 being fabricated in CMOS compatible processes. The program selector 17 can be constructed from a diode that can be embodied as a junction diode with at least one P+ active region on an N well, or a diode with P+ and N+ implants on two ends of a polysilicon substrate or active region on an insulated substrate. The NVM element 16 is commonly an electrical fuse based on polysilicon, silicided polysilicon, metal, CMOS gate material, or anti-fuse based on gate oxide breakdown.
FIG. 2(c) shows a block diagram of a typical low-pin-count NVM cell 130 for a low-pin-count NVM memory. The NVM cell 130 has one NVM element 131 coupled to a supply voltage VDDP in one end and to a selector 132 in the other end as Vx. The selector 132 can be enabled by asserting a signal Sel. The node Vx can be coupled to a sense amplifier 133 and then to a latch 134 by a signal RE. For low-pin-count NVMs, there may be some advantages to build a sense amplifier and a latch into each cell to save the overall costs in a macro and for ease to use.
FIG. 3 shows a pin configuration of a conventional serial OTP memory 20. The OTP memory 20 has an OTP memory module 22 and a power-switch device 21 that couples to a high voltage supply VDDP and the OTP memory module 22. The OTP memory 22 has a chip enable, program, clock, power-switch select, and an output signal denoted as CS#, PGM, CLK, PSWS, and Q, respectively. CS# selects the OTP memory 22 for either read or program. PGM is for program or read control. CLK is for clocking the memory 22. PSWS is for turning on an optional device, power-switch device 21. The output signal Q is for outputting data. Since there are several I/O pins, the footprint of an OTP memory to be integrated into an integrated circuit is large and the cost is relatively high. Sometimes, the PSWS signal can be generated from the OTP memory 22.
FIG. 4(a) shows a program timing waveform of a serial OTP memory with the I/O pin configurations as shown in FIG. 3. If the CLK is low and PGM is high when the CS# falls, the OTP goes into a program mode. Then, PGM toggles to high before the rising edges of CLK for those bits to be programmed. The high CLK period is the actual program time. Similarly, FIG. 4(b) shows a read timing waveform of a serial OTP memory with the I/O pin configurations shown in FIG. 3. If the CLK is high and PGM is low when CS# falls, the OTP goes into a read mode. The cell data are read out at the falling edges of CLK one by one. These timing waveforms in FIGS. 4(a) and 4(b) are relatively complicated.
Another similar low-pin-count I/O interface is the Serial Peripheral Interconnect (SPI) that has CSB, SCLK, SIN, and SO pins for chip select, serial clock, serial input, and serial output, respectively. The timing waveforms of SPI are similar to those in FIGS. 4(a) and 4(b). Another two-pin serial I/O interface is I2C that has only two pins: SDA and SCL, for serial data and serial clock, respectively. This I/O interface is for SRAM-like devices that have comparable read and write access time. The I2C for programming a byte or a page in a serial EEPROM is quite complicated: upon issuing a start bit, device ID, program bit, start address, and stop bit, the chip goes into hibernation so that an internally generated programming can be performed for about 4-8 ms. A status register can be checked for completion before next program commands can be issued again. In an OTP memory, the program time is several orders of magnitude higher than the read access and much lower than either the program or erase time of an EEPROM, for example 1 us for OTP programming versus 50 ns for OTP read and 1 us for OTP programming versus 4 ms for flash programming/erasing, such that I2C interface for OTP is not desirable because of high timing overhead.
As NVM memory sizes continue to be reduced, the number of external interface pins becomes a limitation to the NVM memory size. The conventional serial interfaces are relatively complex and are not able to effectively accommodate read and program speed discrepancies. Accordingly, there is a need for a low-pin-count interface for non-volatile memory, such as OTP memory.